IBIS Macromodel Task Group
Meeting date: 26 March 2024
Members (asterisk for those attending):
Achronix Semiconductor: Hansel Dsilva
Amazon: John Yan
ANSYS: * Curtis Clark
* Wei-hsing Huang
Aurora System: Dian Yang
Raj Raghuram
Cadence Design Systems: * Ambrish Varma
* Jared James
Dassault Systemes: Longfei Bai
Google: Hanfeng Wang
GaWon Kim
Intel: * Michael Mirmak
Kinger Cai
Chi-te Chen
Liwei Zhao
Alaeddin Aydiner
Keysight Technologies: Fangyi Rao
Majid Ahadi Dolatsara
Stephen Slater
Ming Yan
Rui Yang
Marvell: Steve Parker
Mathworks (SiSoft): Walter Katz
Graham Kus
Micron Technology: Justin Butterfield
Missouri S&T: Chulsoon Hwang
Yifan Ding
Zhiping Yang
Rivos: Yansheng Wang
SAE ITC: Michael McNair
Siemens EDA (Mentor): * Arpad Muranyi
* Randy Wolff
Teraspeed Labs: [Bob Ross]
Zuken USA: Lance Wang
The meeting was led by Arpad Muranyi. Curtis Clark took the minutes.
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Opens:
- None.
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Review of ARs:
Michael: Submit the "Definitions Section" proposal to the Open Forum as an
official BIRD.
- Done. It was submitted as BIRD230.
Michael: Send draft4 of the Block Clarification proposal to the ATM list.
- Done.
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Call for patent disclosure:
- None.
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Review of Meeting Minutes:
Arpad asked for any comments or corrections to the minutes of the March 19th
meeting. Michael moved to approve the minutes. Randy seconded the motion.
There were no objections.
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New Discussion:
Block Clarification proposal:
Michael reviewed draft4 of the proposal, which he had sent to the ATM list on
Wednesday March 20th. He said that it incorporated all of the changes from the
previous meeting, and he had received no new feedback. Michael noted one
editorial issue. He said a half-sentence had been left at the beginning of the
Background Information/History section and should be removed.
Arpad asked whether the proposal was ready to send to the Open Forum. Michael
moved to submit draft4 (with the editorial correction) to the Open Forum. Jared
seconded. There were no objections.
Fixing [Clock Pins]:
Michael reviewed a presentation on the limitations of the [Clock Pins] keyword.
In 2021, BIRD208 introduced [Clock Pins] into IBIS 7.1.
Michael said the original intent of [Clock Pins] was to specify which clock pins
latch which data pins. A third column provides a string that could be used to
define the timing relationship, though the only allowed value as of IBIS 7.2
is "Unspecified". A limitation of [Clock Pins], which was only recognized after
BIRD208 was approved, is that the clock pin to data pin relationships are fixed
and defined at the time the .ibs file is created. Therefore, controllers are
not easily supported. A controller might have multiple modes. A single clock
line might support 4 data lines (nibble) in one mode and support 8 data lines
(byte) in another mode.
Michael noted that [Pin]s may have [Model Selector]s. He said we need an
analogous clock selector. Michael proposed a new solution that repurposes the
third column in the [Clock Pins] keyword. The third column could contain a
value indicating a grouping, which could serve as a clock selector. Michael
reviewed a [Clock Pins] example illustrating the nibble and byte cases in the
same [Clock Pins] keyword using different "x4" and "x8" groupings.
[Clock Pins] clocked_pins relationship
A1 B1 x4 | Pins B1, B2, B3, B4 use clock information from A1
A1 B2 x4 | and can be organized as x4
A1 B3 x4
A1 B4 x4
A2 B5 x4 | Pins B5, B6, B7, B8 use clock information from A2
A2 B6 x4 | and can be organized as x4
A2 B7 x4
A2 B8 x4
|
A1 B1 x8 | Pins B1, B2, B3, B4
A1 B2 x8 | B5, B6, B7, B8 use clock information from A1
A1 B3 x8 | and can be organized as x8
A1 B4 x8
A1 B5 x8
A1 B6 x8
A1 B7 x8
A1 B8 x8
Michael said this would be legal with the existing definition of [Clock Pins],
except for the fact that "Unspecified" is currently the only allowed value in
column 3.
Arpad asked whether [Model Selector]s themselves could cause problems for the
timing relationship specifications. Could choosing a different [Model] for a
[Pin] affect the timing relationships we want to define with [Clock Pins]?
Michael said he didn't think that would affect the clock pin to data pin
relationship being defined by the clock selector, but it might be possible that
a selected [Model] would fail to meet some timing requirements for that
relationship. He noted that we hadn't yet gotten to the point of specifying any
timing requirements.
Michael said we would remove the following sentence from IBIS 7.2, if we adopt
his proposed change to the usage of the third column:
The structure of [Clock Pins] assumes that the clocking relationships cannot
be redefined dynamically for the given [Component] (for example, the number
of data pins supported by any one clock pin is fixed).
Arpad said we have to be careful about the language. Even with the proposed
change, we still won't support dynamically changing the clocking relationships
during simulation. We will allow the selection of a configuration prior to
a given simulation.
Michael said that one possible drawback to his proposal is that using the third
column as group/clock selector might conflict with the original intent of
specifying the actual timing relationships (e.g., clock skews, etc.).
Michael closed with a call for feedback. He said the larger questions still
remaining are what timing relationships to specify and how to specify them.
Can we use values, or do we need equations? How do we reference expected timing
relationships but handle manufacturing variations or variable configurations?
How do we reference timing relationships that are strict requirements to
enforce?
Ambrish asked whether there was any precedent for having this type of timing
information in IBIS. He asked whether this information should come from a
higher level protocol or system specification. Michael replied that Vinh and
Vinl fulfill a similar purpose, although in a much more simplistic manner. The
goal is to provide additional information useful for evaluating whether an
interface is working.
- Michael: Motion to adjourn.
- Ambrish: Second.
- Arpad: Thank you all for joining.
New ARs:
None.
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Next meeting: 02 April 2024 12:00pm PT
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IBIS Interconnect SPICE Wish List:
1) Simulator directives